Radiation tolerance and performance of planar pixel assemblies for the Phase-2 Upgrade of the CMS Inner Tracker

Abstract

The aim of this work is to evaluate the performance of planar hybrid pixel detectors designed for the High-Luminosity (HL-LHC) Upgrade of the Inner Tracker of the Compact Muon Solenoid (CMS) experiment at CERN. The HL-LHC will deliver a peak instantaneous luminosity of 7.5 × 10^34 cm^−2 s^−1, resulting in a total expected fluence for planar sensors of around ϕeq = 1 × 10^16 cm^−2 after an integrated luminosity of 3000 fb^−1.

To operate under such extreme radiation levels and high track densities, the new n+-in-p sensors will feature pixels with pitches of 25 × 100 µm^2, covering an area six times smaller than their Phase-1 counterparts. This work focuses on the characterization of 150 µm thick planar sensors manufactured by Hamamatsu Photonics K.K. These sensors are bump-bonded to the RD53B CMS readout chip and tested using a 5.2 GeV electron beam at the DESY II test beam facility. Key observables such as cluster size, noise, threshold, hit efficiency, and spatial resolution are measured as a function of both the applied bias voltage and the beam incidence angle.

The modules are characterized before and after irradiation with 24 GeV/c protons to fluences up to ϕeq = 1 × 10^16 cm^−2. For perpendicular incidence, hit efficiencies exceeding the corresponding fluence-dependent benchmarks are achieved for bias voltages as low as 5 V before irradiation, and in the range of 400 V–500 V after irradiation, for all thresholds under study, while keeping the amount of disabled pixels below the 1% limit, fulfilling the requirements for the second layer of the Phase-2 pixel detector. These measurements reveal that the optimal efficiency is achieved for a charge threshold of 1200 e− and a bias voltage of 600 V for all investigated fluences.

A spatial resolution of circa 3 µm was measured before irradiation at the optimal track incidence angle, degrading to about 4 µm after irradiation to the highest fluence under exam.

The characterization of these assemblies included in-depth studies of the correlation between crosstalk and readout timing in the first half-size demonstrator (RD53A) and in the pre-series version of the chips (RD53B CMS). By using the integrated charge injection circuit, crosstalk levels well-below the established 10% limit were measured for the optimal readout scheme, meeting the associated requirement.